Analysis & Synthesis report for DE0_NANO
Thu Aug 09 00:24:37 2018
Quartus Prime Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis RAM Summary
  9. Analysis & Synthesis IP Cores Summary
 10. Registers Removed During Synthesis
 11. Removed Registers Triggering Further Register Optimizations
 12. General Register Statistics
 13. Registers Packed Into Inferred Megafunctions
 14. Multiplexer Restructuring Statistics (Restructuring Performed)
 15. Source assignments for Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0|altsyncram_k5f1:auto_generated
 16. Parameter Settings for User Entity Instance: PLL:PLL_inst|altpll:altpll_component
 17. Parameter Settings for Inferred Entity Instance: Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0
 18. Parameter Settings for Inferred Entity Instance: lpm_mult:Mult0
 19. Parameter Settings for Inferred Entity Instance: lpm_mult:Mult1
 20. altpll Parameter Settings by Entity Instance
 21. altsyncram Parameter Settings by Entity Instance
 22. lpm_mult Parameter Settings by Entity Instance
 23. Port Connectivity Checks: "IMAGE_PROCESSOR:proc"
 24. Post-Synthesis Netlist Statistics for Top Partition
 25. Elapsed Time Per Partition
 26. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 2017  Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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applicable license agreement, including, without limitation, 
that your use is for the sole purpose of programming logic 
devices manufactured by Intel and sold by Intel or its 
authorized distributors.  Please refer to the applicable 
agreement for further details.



+----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                     ;
+------------------------------------+---------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Thu Aug 09 00:24:37 2018       ;
; Quartus Prime Version              ; 17.0.0 Build 595 04/25/2017 SJ Lite Edition ;
; Revision Name                      ; DE0_NANO                                    ;
; Top-level Entity Name              ; DE0_NANO                                    ;
; Family                             ; Cyclone IV E                                ;
; Total logic elements               ; 181                                         ;
;     Total combinational functions  ; 172                                         ;
;     Dedicated logic registers      ; 59                                          ;
; Total registers                    ; 59                                          ;
; Total pins                         ; 51                                          ;
; Total virtual pins                 ; 0                                           ;
; Total memory bits                  ; 202,752                                     ;
; Embedded Multiplier 9-bit elements ; 0                                           ;
; Total PLLs                         ; 1                                           ;
+------------------------------------+---------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                        ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                     ; Setting            ; Default Value      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                     ; EP4CE22F17C6       ;                    ;
; Top-level entity name                                                      ; DE0_NANO           ; DE0_NANO           ;
; Family name                                                                ; Cyclone IV E       ; Cyclone IV GX      ;
; Use smart compilation                                                      ; Off                ; Off                ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                                ; Off                ; Off                ;
; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
; Preserve fewer node names                                                  ; On                 ; On                 ;
; OpenCore Plus hardware evaluation                                          ; Enable             ; Enable             ;
; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                   ; Auto               ; Auto               ;
; Safe State Machine                                                         ; Off                ; Off                ;
; Extract Verilog State Machines                                             ; On                 ; On                 ;
; Extract VHDL State Machines                                                ; On                 ; On                 ;
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
; Parallel Synthesis                                                         ; On                 ; On                 ;
; DSP Block Balancing                                                        ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                         ; On                 ; On                 ;
; Power-Up Don't Care                                                        ; On                 ; On                 ;
; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
; Remove Duplicate Registers                                                 ; On                 ; On                 ;
; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
; Optimization Technique                                                     ; Balanced           ; Balanced           ;
; Carry Chain Length                                                         ; 70                 ; 70                 ;
; Auto Carry Chains                                                          ; On                 ; On                 ;
; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
; Auto ROM Replacement                                                       ; On                 ; On                 ;
; Auto RAM Replacement                                                       ; On                 ; On                 ;
; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
; Strict RAM Replacement                                                     ; Off                ; Off                ;
; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                      ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
; Report Parameter Settings                                                  ; On                 ; On                 ;
; Report Source Assignments                                                  ; On                 ; On                 ;
; Report Connectivity Checks                                                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
; PowerPlay Power Optimization During Synthesis                              ; Normal compilation ; Normal compilation ;
; HDL message level                                                          ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
; Clock MUX Protection                                                       ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
; Block Design Naming                                                        ; Auto               ; Auto               ;
; SDC constraint protection                                                  ; Off                ; Off                ;
; Synthesis Effort                                                           ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
+----------------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 8           ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 4           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processors 2-4         ;   0.0%      ;
+----------------------------+-------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                           ;
+----------------------------------+-----------------+------------------------------+------------------------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                                       ; Library ;
+----------------------------------+-----------------+------------------------------+------------------------------------------------------------------------------------+---------+
; VGA_DRIVER.v                     ; yes             ; User Verilog HDL File        ; C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/VGA_DRIVER.v           ;         ;
; DE0_NANO.v                       ; yes             ; User Verilog HDL File        ; C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v             ;         ;
; Dual_Port_RAM_M9K.v              ; yes             ; User Verilog HDL File        ; C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/Dual_Port_RAM_M9K.v    ;         ;
; IMAGE_PROCESSOR.v                ; yes             ; User Verilog HDL File        ; C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/IMAGE_PROCESSOR.v      ;         ;
; PLL.v                            ; yes             ; User Wizard-Generated File   ; C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/PLL.v                  ;         ;
; altpll.tdf                       ; yes             ; Megafunction                 ; c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/altpll.tdf                  ;         ;
; aglobal170.inc                   ; yes             ; Megafunction                 ; c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/aglobal170.inc              ;         ;
; stratix_pll.inc                  ; yes             ; Megafunction                 ; c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/stratix_pll.inc             ;         ;
; stratixii_pll.inc                ; yes             ; Megafunction                 ; c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/stratixii_pll.inc           ;         ;
; cycloneii_pll.inc                ; yes             ; Megafunction                 ; c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/cycloneii_pll.inc           ;         ;
; db/pll_altpll.v                  ; yes             ; Auto-Generated Megafunction  ; C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/db/pll_altpll.v        ;         ;
; altsyncram.tdf                   ; yes             ; Megafunction                 ; c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/altsyncram.tdf              ;         ;
; stratix_ram_block.inc            ; yes             ; Megafunction                 ; c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/stratix_ram_block.inc       ;         ;
; lpm_mux.inc                      ; yes             ; Megafunction                 ; c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/lpm_mux.inc                 ;         ;
; lpm_decode.inc                   ; yes             ; Megafunction                 ; c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/lpm_decode.inc              ;         ;
; a_rdenreg.inc                    ; yes             ; Megafunction                 ; c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/a_rdenreg.inc               ;         ;
; altrom.inc                       ; yes             ; Megafunction                 ; c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/altrom.inc                  ;         ;
; altram.inc                       ; yes             ; Megafunction                 ; c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/altram.inc                  ;         ;
; altdpram.inc                     ; yes             ; Megafunction                 ; c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/altdpram.inc                ;         ;
; db/altsyncram_k5f1.tdf           ; yes             ; Auto-Generated Megafunction  ; C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/db/altsyncram_k5f1.tdf ;         ;
; db/decode_msa.tdf                ; yes             ; Auto-Generated Megafunction  ; C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/db/decode_msa.tdf      ;         ;
; db/decode_f8a.tdf                ; yes             ; Auto-Generated Megafunction  ; C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/db/decode_f8a.tdf      ;         ;
; db/mux_6nb.tdf                   ; yes             ; Auto-Generated Megafunction  ; C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/db/mux_6nb.tdf         ;         ;
; lpm_mult.tdf                     ; yes             ; Megafunction                 ; c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/lpm_mult.tdf                ;         ;
; lpm_add_sub.inc                  ; yes             ; Megafunction                 ; c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/lpm_add_sub.inc             ;         ;
; multcore.inc                     ; yes             ; Megafunction                 ; c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/multcore.inc                ;         ;
; bypassff.inc                     ; yes             ; Megafunction                 ; c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/bypassff.inc                ;         ;
; altshift.inc                     ; yes             ; Megafunction                 ; c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/altshift.inc                ;         ;
; multcore.tdf                     ; yes             ; Megafunction                 ; c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/multcore.tdf                ;         ;
; csa_add.inc                      ; yes             ; Megafunction                 ; c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/csa_add.inc                 ;         ;
; mpar_add.inc                     ; yes             ; Megafunction                 ; c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/mpar_add.inc                ;         ;
; muleabz.inc                      ; yes             ; Megafunction                 ; c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/muleabz.inc                 ;         ;
; mul_lfrg.inc                     ; yes             ; Megafunction                 ; c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/mul_lfrg.inc                ;         ;
; mul_boothc.inc                   ; yes             ; Megafunction                 ; c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/mul_boothc.inc              ;         ;
; alt_ded_mult.inc                 ; yes             ; Megafunction                 ; c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/alt_ded_mult.inc            ;         ;
; alt_ded_mult_y.inc               ; yes             ; Megafunction                 ; c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/alt_ded_mult_y.inc          ;         ;
; dffpipe.inc                      ; yes             ; Megafunction                 ; c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/dffpipe.inc                 ;         ;
; mpar_add.tdf                     ; yes             ; Megafunction                 ; c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/mpar_add.tdf                ;         ;
; lpm_add_sub.tdf                  ; yes             ; Megafunction                 ; c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/lpm_add_sub.tdf             ;         ;
; addcore.inc                      ; yes             ; Megafunction                 ; c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/addcore.inc                 ;         ;
; look_add.inc                     ; yes             ; Megafunction                 ; c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/look_add.inc                ;         ;
; alt_stratix_add_sub.inc          ; yes             ; Megafunction                 ; c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/alt_stratix_add_sub.inc     ;         ;
; db/add_sub_lgh.tdf               ; yes             ; Auto-Generated Megafunction  ; C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/db/add_sub_lgh.tdf     ;         ;
; db/add_sub_pgh.tdf               ; yes             ; Auto-Generated Megafunction  ; C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/db/add_sub_pgh.tdf     ;         ;
; altshift.tdf                     ; yes             ; Megafunction                 ; c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/altshift.tdf                ;         ;
+----------------------------------+-----------------+------------------------------+------------------------------------------------------------------------------------+---------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                                                                                   ;
+---------------------------------------------+---------------------------------------------------------------------------------+
; Resource                                    ; Usage                                                                           ;
+---------------------------------------------+---------------------------------------------------------------------------------+
; Estimated Total logic elements              ; 181                                                                             ;
;                                             ;                                                                                 ;
; Total combinational functions               ; 172                                                                             ;
; Logic element usage by number of LUT inputs ;                                                                                 ;
;     -- 4 input functions                    ; 48                                                                              ;
;     -- 3 input functions                    ; 49                                                                              ;
;     -- <=2 input functions                  ; 75                                                                              ;
;                                             ;                                                                                 ;
; Logic elements by mode                      ;                                                                                 ;
;     -- normal mode                          ; 94                                                                              ;
;     -- arithmetic mode                      ; 78                                                                              ;
;                                             ;                                                                                 ;
; Total registers                             ; 59                                                                              ;
;     -- Dedicated logic registers            ; 59                                                                              ;
;     -- I/O registers                        ; 0                                                                               ;
;                                             ;                                                                                 ;
; I/O pins                                    ; 51                                                                              ;
; Total memory bits                           ; 202752                                                                          ;
;                                             ;                                                                                 ;
; Embedded Multiplier 9-bit elements          ; 0                                                                               ;
;                                             ;                                                                                 ;
; Total PLLs                                  ; 1                                                                               ;
;     -- PLLs                                 ; 1                                                                               ;
;                                             ;                                                                                 ;
; Maximum fan-out node                        ; PLL:PLL_inst|altpll:altpll_component|PLL_altpll:auto_generated|wire_pll1_clk[0] ;
; Maximum fan-out                             ; 57                                                                              ;
; Total fan-out                               ; 1667                                                                            ;
; Average fan-out                             ; 4.55                                                                            ;
+---------------------------------------------+---------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                             ;
+------------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------+-------------------+--------------+
; Compilation Hierarchy Node                     ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                              ; Entity Name       ; Library Name ;
+------------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------+-------------------+--------------+
; |DE0_NANO                                      ; 172 (53)            ; 59 (37)                   ; 202752      ; 0            ; 0       ; 0         ; 51   ; 0            ; |DE0_NANO                                                                                                                        ; DE0_NANO          ; work         ;
;    |Dual_Port_RAM_M9K:mem|                     ; 8 (0)               ; 2 (0)                     ; 202752      ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE0_NANO|Dual_Port_RAM_M9K:mem                                                                                                  ; Dual_Port_RAM_M9K ; work         ;
;       |altsyncram:mem_rtl_0|                   ; 8 (0)               ; 2 (0)                     ; 202752      ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE0_NANO|Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0                                                                             ; altsyncram        ; work         ;
;          |altsyncram_k5f1:auto_generated|      ; 8 (0)               ; 2 (2)                     ; 202752      ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE0_NANO|Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0|altsyncram_k5f1:auto_generated                                              ; altsyncram_k5f1   ; work         ;
;             |decode_f8a:rden_decode_b|         ; 4 (4)               ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE0_NANO|Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0|altsyncram_k5f1:auto_generated|decode_f8a:rden_decode_b                     ; decode_f8a        ; work         ;
;             |decode_msa:decode2|               ; 4 (4)               ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE0_NANO|Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0|altsyncram_k5f1:auto_generated|decode_msa:decode2                           ; decode_msa        ; work         ;
;    |PLL:PLL_inst|                              ; 0 (0)               ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE0_NANO|PLL:PLL_inst                                                                                                           ; PLL               ; work         ;
;       |altpll:altpll_component|                ; 0 (0)               ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE0_NANO|PLL:PLL_inst|altpll:altpll_component                                                                                   ; altpll            ; work         ;
;          |PLL_altpll:auto_generated|           ; 0 (0)               ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE0_NANO|PLL:PLL_inst|altpll:altpll_component|PLL_altpll:auto_generated                                                         ; PLL_altpll        ; work         ;
;    |VGA_DRIVER:driver|                         ; 60 (60)             ; 20 (20)                   ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE0_NANO|VGA_DRIVER:driver                                                                                                      ; VGA_DRIVER        ; work         ;
;    |lpm_mult:Mult0|                            ; 25 (0)              ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE0_NANO|lpm_mult:Mult0                                                                                                         ; lpm_mult          ; work         ;
;       |multcore:mult_core|                     ; 25 (15)             ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE0_NANO|lpm_mult:Mult0|multcore:mult_core                                                                                      ; multcore          ; work         ;
;          |mpar_add:padder|                     ; 10 (0)              ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE0_NANO|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder                                                                      ; mpar_add          ; work         ;
;             |lpm_add_sub:adder[0]|             ; 7 (0)               ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE0_NANO|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]                                                 ; lpm_add_sub       ; work         ;
;                |add_sub_lgh:auto_generated|    ; 7 (7)               ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE0_NANO|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_lgh:auto_generated                      ; add_sub_lgh       ; work         ;
;             |mpar_add:sub_par_add|             ; 3 (0)               ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE0_NANO|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add                                                 ; mpar_add          ; work         ;
;                |lpm_add_sub:adder[0]|          ; 3 (0)               ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE0_NANO|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]                            ; lpm_add_sub       ; work         ;
;                   |add_sub_pgh:auto_generated| ; 3 (3)               ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE0_NANO|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_pgh:auto_generated ; add_sub_pgh       ; work         ;
;    |lpm_mult:Mult1|                            ; 26 (0)              ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE0_NANO|lpm_mult:Mult1                                                                                                         ; lpm_mult          ; work         ;
;       |multcore:mult_core|                     ; 26 (16)             ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE0_NANO|lpm_mult:Mult1|multcore:mult_core                                                                                      ; multcore          ; work         ;
;          |mpar_add:padder|                     ; 10 (0)              ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE0_NANO|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder                                                                      ; mpar_add          ; work         ;
;             |lpm_add_sub:adder[0]|             ; 7 (0)               ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE0_NANO|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]                                                 ; lpm_add_sub       ; work         ;
;                |add_sub_lgh:auto_generated|    ; 7 (7)               ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE0_NANO|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_lgh:auto_generated                      ; add_sub_lgh       ; work         ;
;             |mpar_add:sub_par_add|             ; 3 (0)               ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE0_NANO|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add                                                 ; mpar_add          ; work         ;
;                |lpm_add_sub:adder[0]|          ; 3 (0)               ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE0_NANO|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]                            ; lpm_add_sub       ; work         ;
;                   |add_sub_pgh:auto_generated| ; 3 (3)               ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE0_NANO|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_pgh:auto_generated ; add_sub_pgh       ; work         ;
+------------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------+-------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                           ;
+--------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+------+
; Name                                                                                 ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size   ; MIF  ;
+--------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+------+
; Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0|altsyncram_k5f1:auto_generated|ALTSYNCRAM ; M9K  ; Simple Dual Port ; 25344        ; 8            ; 25344        ; 8            ; 202752 ; None ;
+--------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+------+


+----------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary                                                                    ;
+--------+--------------+---------+--------------+--------------+------------------------+-----------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance        ; IP Include File ;
+--------+--------------+---------+--------------+--------------+------------------------+-----------------+
; Altera ; ALTPLL       ; 17.0    ; N/A          ; N/A          ; |DE0_NANO|PLL:PLL_inst ; PLL.v           ;
+--------+--------------+---------+--------------+--------------+------------------------+-----------------+


+------------------------------------------------------------+
; Registers Removed During Synthesis                         ;
+---------------------------------------+--------------------+
; Register name                         ; Reason for Removal ;
+---------------------------------------+--------------------+
; Y_ADDR[11..14]                        ; Lost fanout        ;
; Total Number of Removed Registers = 4 ;                    ;
+---------------------------------------+--------------------+


+-----------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations                 ;
+---------------+--------------------+----------------------------------------+
; Register name ; Reason for Removal ; Registers Removed due to This Register ;
+---------------+--------------------+----------------------------------------+
; Y_ADDR[12]    ; Lost Fanouts       ; Y_ADDR[11]                             ;
+---------------+--------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 59    ;
; Number of registers using Synchronous Clear  ; 46    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 44    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+----------------------------------------------------------------------------------+
; Registers Packed Into Inferred Megafunctions                                     ;
+-----------------------------------------+---------------------------------+------+
; Register Name                           ; Megafunction                    ; Type ;
+-----------------------------------------+---------------------------------+------+
; Dual_Port_RAM_M9K:mem|output_data[0..7] ; Dual_Port_RAM_M9K:mem|mem_rtl_0 ; RAM  ;
+-----------------------------------------+---------------------------------+------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                               ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                     ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------+
; 3:1                ; 10 bits   ; 20 LEs        ; 10 LEs               ; 10 LEs                 ; Yes        ; |DE0_NANO|VGA_DRIVER:driver|pixel_count[3]     ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |DE0_NANO|W_EN                                 ;
; 4:1                ; 15 bits   ; 30 LEs        ; 15 LEs               ; 15 LEs                 ; Yes        ; |DE0_NANO|X_ADDR[13]                           ;
; 3:1                ; 15 bits   ; 30 LEs        ; 15 LEs               ; 15 LEs                 ; Yes        ; |DE0_NANO|Y_ADDR[7]                            ;
; 4:1                ; 10 bits   ; 20 LEs        ; 10 LEs               ; 10 LEs                 ; Yes        ; |DE0_NANO|VGA_DRIVER:driver|line_count[9]      ;
; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; No         ; |DE0_NANO|VGA_DRIVER:driver|PIXEL_COLOR_OUT[6] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------+


+--------------------------------------------------------------------------------------------------+
; Source assignments for Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0|altsyncram_k5f1:auto_generated ;
+---------------------------------+--------------------+------+------------------------------------+
; Assignment                      ; Value              ; From ; To                                 ;
+---------------------------------+--------------------+------+------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                  ;
+---------------------------------+--------------------+------+------------------------------------+


+-----------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: PLL:PLL_inst|altpll:altpll_component ;
+-------------------------------+-----------------------+---------------------------+
; Parameter Name                ; Value                 ; Type                      ;
+-------------------------------+-----------------------+---------------------------+
; OPERATION_MODE                ; NORMAL                ; Untyped                   ;
; PLL_TYPE                      ; AUTO                  ; Untyped                   ;
; LPM_HINT                      ; CBX_MODULE_PREFIX=PLL ; Untyped                   ;
; QUALIFY_CONF_DONE             ; OFF                   ; Untyped                   ;
; COMPENSATE_CLOCK              ; CLK0                  ; Untyped                   ;
; SCAN_CHAIN                    ; LONG                  ; Untyped                   ;
; PRIMARY_CLOCK                 ; INCLK0                ; Untyped                   ;
; INCLK0_INPUT_FREQUENCY        ; 20000                 ; Signed Integer            ;
; INCLK1_INPUT_FREQUENCY        ; 0                     ; Untyped                   ;
; GATE_LOCK_SIGNAL              ; NO                    ; Untyped                   ;
; GATE_LOCK_COUNTER             ; 0                     ; Untyped                   ;
; LOCK_HIGH                     ; 1                     ; Untyped                   ;
; LOCK_LOW                      ; 1                     ; Untyped                   ;
; VALID_LOCK_MULTIPLIER         ; 1                     ; Untyped                   ;
; INVALID_LOCK_MULTIPLIER       ; 5                     ; Untyped                   ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF                   ; Untyped                   ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF                   ; Untyped                   ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF                   ; Untyped                   ;
; SKIP_VCO                      ; OFF                   ; Untyped                   ;
; SWITCH_OVER_COUNTER           ; 0                     ; Untyped                   ;
; SWITCH_OVER_TYPE              ; AUTO                  ; Untyped                   ;
; FEEDBACK_SOURCE               ; EXTCLK0               ; Untyped                   ;
; BANDWIDTH                     ; 0                     ; Untyped                   ;
; BANDWIDTH_TYPE                ; AUTO                  ; Untyped                   ;
; SPREAD_FREQUENCY              ; 0                     ; Untyped                   ;
; DOWN_SPREAD                   ; 0                     ; Untyped                   ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF                   ; Untyped                   ;
; SELF_RESET_ON_LOSS_LOCK       ; OFF                   ; Untyped                   ;
; CLK9_MULTIPLY_BY              ; 0                     ; Untyped                   ;
; CLK8_MULTIPLY_BY              ; 0                     ; Untyped                   ;
; CLK7_MULTIPLY_BY              ; 0                     ; Untyped                   ;
; CLK6_MULTIPLY_BY              ; 0                     ; Untyped                   ;
; CLK5_MULTIPLY_BY              ; 1                     ; Untyped                   ;
; CLK4_MULTIPLY_BY              ; 1                     ; Untyped                   ;
; CLK3_MULTIPLY_BY              ; 1                     ; Untyped                   ;
; CLK2_MULTIPLY_BY              ; 1                     ; Signed Integer            ;
; CLK1_MULTIPLY_BY              ; 1                     ; Signed Integer            ;
; CLK0_MULTIPLY_BY              ; 12                    ; Signed Integer            ;
; CLK9_DIVIDE_BY                ; 0                     ; Untyped                   ;
; CLK8_DIVIDE_BY                ; 0                     ; Untyped                   ;
; CLK7_DIVIDE_BY                ; 0                     ; Untyped                   ;
; CLK6_DIVIDE_BY                ; 0                     ; Untyped                   ;
; CLK5_DIVIDE_BY                ; 1                     ; Untyped                   ;
; CLK4_DIVIDE_BY                ; 1                     ; Untyped                   ;
; CLK3_DIVIDE_BY                ; 1                     ; Untyped                   ;
; CLK2_DIVIDE_BY                ; 1                     ; Signed Integer            ;
; CLK1_DIVIDE_BY                ; 2                     ; Signed Integer            ;
; CLK0_DIVIDE_BY                ; 25                    ; Signed Integer            ;
; CLK9_PHASE_SHIFT              ; 0                     ; Untyped                   ;
; CLK8_PHASE_SHIFT              ; 0                     ; Untyped                   ;
; CLK7_PHASE_SHIFT              ; 0                     ; Untyped                   ;
; CLK6_PHASE_SHIFT              ; 0                     ; Untyped                   ;
; CLK5_PHASE_SHIFT              ; 0                     ; Untyped                   ;
; CLK4_PHASE_SHIFT              ; 0                     ; Untyped                   ;
; CLK3_PHASE_SHIFT              ; 0                     ; Untyped                   ;
; CLK2_PHASE_SHIFT              ; 0                     ; Untyped                   ;
; CLK1_PHASE_SHIFT              ; 0                     ; Untyped                   ;
; CLK0_PHASE_SHIFT              ; 0                     ; Untyped                   ;
; CLK5_TIME_DELAY               ; 0                     ; Untyped                   ;
; CLK4_TIME_DELAY               ; 0                     ; Untyped                   ;
; CLK3_TIME_DELAY               ; 0                     ; Untyped                   ;
; CLK2_TIME_DELAY               ; 0                     ; Untyped                   ;
; CLK1_TIME_DELAY               ; 0                     ; Untyped                   ;
; CLK0_TIME_DELAY               ; 0                     ; Untyped                   ;
; CLK9_DUTY_CYCLE               ; 50                    ; Untyped                   ;
; CLK8_DUTY_CYCLE               ; 50                    ; Untyped                   ;
; CLK7_DUTY_CYCLE               ; 50                    ; Untyped                   ;
; CLK6_DUTY_CYCLE               ; 50                    ; Untyped                   ;
; CLK5_DUTY_CYCLE               ; 50                    ; Untyped                   ;
; CLK4_DUTY_CYCLE               ; 50                    ; Untyped                   ;
; CLK3_DUTY_CYCLE               ; 50                    ; Untyped                   ;
; CLK2_DUTY_CYCLE               ; 50                    ; Signed Integer            ;
; CLK1_DUTY_CYCLE               ; 50                    ; Signed Integer            ;
; CLK0_DUTY_CYCLE               ; 50                    ; Signed Integer            ;
; CLK9_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                   ;
; CLK8_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                   ;
; CLK7_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                   ;
; CLK6_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                   ;
; CLK5_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                   ;
; CLK4_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                   ;
; CLK3_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                   ;
; CLK2_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                   ;
; CLK1_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                   ;
; CLK0_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped                   ;
; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                   ;
; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                   ;
; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                   ;
; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                   ;
; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                   ;
; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                   ;
; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                   ;
; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                   ;
; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                   ;
; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped                   ;
; LOCK_WINDOW_UI                ;  0.05                 ; Untyped                   ;
; LOCK_WINDOW_UI_BITS           ; UNUSED                ; Untyped                   ;
; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED                ; Untyped                   ;
; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED                ; Untyped                   ;
; DPA_MULTIPLY_BY               ; 0                     ; Untyped                   ;
; DPA_DIVIDE_BY                 ; 1                     ; Untyped                   ;
; DPA_DIVIDER                   ; 0                     ; Untyped                   ;
; EXTCLK3_MULTIPLY_BY           ; 1                     ; Untyped                   ;
; EXTCLK2_MULTIPLY_BY           ; 1                     ; Untyped                   ;
; EXTCLK1_MULTIPLY_BY           ; 1                     ; Untyped                   ;
; EXTCLK0_MULTIPLY_BY           ; 1                     ; Untyped                   ;
; EXTCLK3_DIVIDE_BY             ; 1                     ; Untyped                   ;
; EXTCLK2_DIVIDE_BY             ; 1                     ; Untyped                   ;
; EXTCLK1_DIVIDE_BY             ; 1                     ; Untyped                   ;
; EXTCLK0_DIVIDE_BY             ; 1                     ; Untyped                   ;
; EXTCLK3_PHASE_SHIFT           ; 0                     ; Untyped                   ;
; EXTCLK2_PHASE_SHIFT           ; 0                     ; Untyped                   ;
; EXTCLK1_PHASE_SHIFT           ; 0                     ; Untyped                   ;
; EXTCLK0_PHASE_SHIFT           ; 0                     ; Untyped                   ;
; EXTCLK3_TIME_DELAY            ; 0                     ; Untyped                   ;
; EXTCLK2_TIME_DELAY            ; 0                     ; Untyped                   ;
; EXTCLK1_TIME_DELAY            ; 0                     ; Untyped                   ;
; EXTCLK0_TIME_DELAY            ; 0                     ; Untyped                   ;
; EXTCLK3_DUTY_CYCLE            ; 50                    ; Untyped                   ;
; EXTCLK2_DUTY_CYCLE            ; 50                    ; Untyped                   ;
; EXTCLK1_DUTY_CYCLE            ; 50                    ; Untyped                   ;
; EXTCLK0_DUTY_CYCLE            ; 50                    ; Untyped                   ;
; VCO_MULTIPLY_BY               ; 0                     ; Untyped                   ;
; VCO_DIVIDE_BY                 ; 0                     ; Untyped                   ;
; SCLKOUT0_PHASE_SHIFT          ; 0                     ; Untyped                   ;
; SCLKOUT1_PHASE_SHIFT          ; 0                     ; Untyped                   ;
; VCO_MIN                       ; 0                     ; Untyped                   ;
; VCO_MAX                       ; 0                     ; Untyped                   ;
; VCO_CENTER                    ; 0                     ; Untyped                   ;
; PFD_MIN                       ; 0                     ; Untyped                   ;
; PFD_MAX                       ; 0                     ; Untyped                   ;
; M_INITIAL                     ; 0                     ; Untyped                   ;
; M                             ; 0                     ; Untyped                   ;
; N                             ; 1                     ; Untyped                   ;
; M2                            ; 1                     ; Untyped                   ;
; N2                            ; 1                     ; Untyped                   ;
; SS                            ; 1                     ; Untyped                   ;
; C0_HIGH                       ; 0                     ; Untyped                   ;
; C1_HIGH                       ; 0                     ; Untyped                   ;
; C2_HIGH                       ; 0                     ; Untyped                   ;
; C3_HIGH                       ; 0                     ; Untyped                   ;
; C4_HIGH                       ; 0                     ; Untyped                   ;
; C5_HIGH                       ; 0                     ; Untyped                   ;
; C6_HIGH                       ; 0                     ; Untyped                   ;
; C7_HIGH                       ; 0                     ; Untyped                   ;
; C8_HIGH                       ; 0                     ; Untyped                   ;
; C9_HIGH                       ; 0                     ; Untyped                   ;
; C0_LOW                        ; 0                     ; Untyped                   ;
; C1_LOW                        ; 0                     ; Untyped                   ;
; C2_LOW                        ; 0                     ; Untyped                   ;
; C3_LOW                        ; 0                     ; Untyped                   ;
; C4_LOW                        ; 0                     ; Untyped                   ;
; C5_LOW                        ; 0                     ; Untyped                   ;
; C6_LOW                        ; 0                     ; Untyped                   ;
; C7_LOW                        ; 0                     ; Untyped                   ;
; C8_LOW                        ; 0                     ; Untyped                   ;
; C9_LOW                        ; 0                     ; Untyped                   ;
; C0_INITIAL                    ; 0                     ; Untyped                   ;
; C1_INITIAL                    ; 0                     ; Untyped                   ;
; C2_INITIAL                    ; 0                     ; Untyped                   ;
; C3_INITIAL                    ; 0                     ; Untyped                   ;
; C4_INITIAL                    ; 0                     ; Untyped                   ;
; C5_INITIAL                    ; 0                     ; Untyped                   ;
; C6_INITIAL                    ; 0                     ; Untyped                   ;
; C7_INITIAL                    ; 0                     ; Untyped                   ;
; C8_INITIAL                    ; 0                     ; Untyped                   ;
; C9_INITIAL                    ; 0                     ; Untyped                   ;
; C0_MODE                       ; BYPASS                ; Untyped                   ;
; C1_MODE                       ; BYPASS                ; Untyped                   ;
; C2_MODE                       ; BYPASS                ; Untyped                   ;
; C3_MODE                       ; BYPASS                ; Untyped                   ;
; C4_MODE                       ; BYPASS                ; Untyped                   ;
; C5_MODE                       ; BYPASS                ; Untyped                   ;
; C6_MODE                       ; BYPASS                ; Untyped                   ;
; C7_MODE                       ; BYPASS                ; Untyped                   ;
; C8_MODE                       ; BYPASS                ; Untyped                   ;
; C9_MODE                       ; BYPASS                ; Untyped                   ;
; C0_PH                         ; 0                     ; Untyped                   ;
; C1_PH                         ; 0                     ; Untyped                   ;
; C2_PH                         ; 0                     ; Untyped                   ;
; C3_PH                         ; 0                     ; Untyped                   ;
; C4_PH                         ; 0                     ; Untyped                   ;
; C5_PH                         ; 0                     ; Untyped                   ;
; C6_PH                         ; 0                     ; Untyped                   ;
; C7_PH                         ; 0                     ; Untyped                   ;
; C8_PH                         ; 0                     ; Untyped                   ;
; C9_PH                         ; 0                     ; Untyped                   ;
; L0_HIGH                       ; 1                     ; Untyped                   ;
; L1_HIGH                       ; 1                     ; Untyped                   ;
; G0_HIGH                       ; 1                     ; Untyped                   ;
; G1_HIGH                       ; 1                     ; Untyped                   ;
; G2_HIGH                       ; 1                     ; Untyped                   ;
; G3_HIGH                       ; 1                     ; Untyped                   ;
; E0_HIGH                       ; 1                     ; Untyped                   ;
; E1_HIGH                       ; 1                     ; Untyped                   ;
; E2_HIGH                       ; 1                     ; Untyped                   ;
; E3_HIGH                       ; 1                     ; Untyped                   ;
; L0_LOW                        ; 1                     ; Untyped                   ;
; L1_LOW                        ; 1                     ; Untyped                   ;
; G0_LOW                        ; 1                     ; Untyped                   ;
; G1_LOW                        ; 1                     ; Untyped                   ;
; G2_LOW                        ; 1                     ; Untyped                   ;
; G3_LOW                        ; 1                     ; Untyped                   ;
; E0_LOW                        ; 1                     ; Untyped                   ;
; E1_LOW                        ; 1                     ; Untyped                   ;
; E2_LOW                        ; 1                     ; Untyped                   ;
; E3_LOW                        ; 1                     ; Untyped                   ;
; L0_INITIAL                    ; 1                     ; Untyped                   ;
; L1_INITIAL                    ; 1                     ; Untyped                   ;
; G0_INITIAL                    ; 1                     ; Untyped                   ;
; G1_INITIAL                    ; 1                     ; Untyped                   ;
; G2_INITIAL                    ; 1                     ; Untyped                   ;
; G3_INITIAL                    ; 1                     ; Untyped                   ;
; E0_INITIAL                    ; 1                     ; Untyped                   ;
; E1_INITIAL                    ; 1                     ; Untyped                   ;
; E2_INITIAL                    ; 1                     ; Untyped                   ;
; E3_INITIAL                    ; 1                     ; Untyped                   ;
; L0_MODE                       ; BYPASS                ; Untyped                   ;
; L1_MODE                       ; BYPASS                ; Untyped                   ;
; G0_MODE                       ; BYPASS                ; Untyped                   ;
; G1_MODE                       ; BYPASS                ; Untyped                   ;
; G2_MODE                       ; BYPASS                ; Untyped                   ;
; G3_MODE                       ; BYPASS                ; Untyped                   ;
; E0_MODE                       ; BYPASS                ; Untyped                   ;
; E1_MODE                       ; BYPASS                ; Untyped                   ;
; E2_MODE                       ; BYPASS                ; Untyped                   ;
; E3_MODE                       ; BYPASS                ; Untyped                   ;
; L0_PH                         ; 0                     ; Untyped                   ;
; L1_PH                         ; 0                     ; Untyped                   ;
; G0_PH                         ; 0                     ; Untyped                   ;
; G1_PH                         ; 0                     ; Untyped                   ;
; G2_PH                         ; 0                     ; Untyped                   ;
; G3_PH                         ; 0                     ; Untyped                   ;
; E0_PH                         ; 0                     ; Untyped                   ;
; E1_PH                         ; 0                     ; Untyped                   ;
; E2_PH                         ; 0                     ; Untyped                   ;
; E3_PH                         ; 0                     ; Untyped                   ;
; M_PH                          ; 0                     ; Untyped                   ;
; C1_USE_CASC_IN                ; OFF                   ; Untyped                   ;
; C2_USE_CASC_IN                ; OFF                   ; Untyped                   ;
; C3_USE_CASC_IN                ; OFF                   ; Untyped                   ;
; C4_USE_CASC_IN                ; OFF                   ; Untyped                   ;
; C5_USE_CASC_IN                ; OFF                   ; Untyped                   ;
; C6_USE_CASC_IN                ; OFF                   ; Untyped                   ;
; C7_USE_CASC_IN                ; OFF                   ; Untyped                   ;
; C8_USE_CASC_IN                ; OFF                   ; Untyped                   ;
; C9_USE_CASC_IN                ; OFF                   ; Untyped                   ;
; CLK0_COUNTER                  ; G0                    ; Untyped                   ;
; CLK1_COUNTER                  ; G0                    ; Untyped                   ;
; CLK2_COUNTER                  ; G0                    ; Untyped                   ;
; CLK3_COUNTER                  ; G0                    ; Untyped                   ;
; CLK4_COUNTER                  ; G0                    ; Untyped                   ;
; CLK5_COUNTER                  ; G0                    ; Untyped                   ;
; CLK6_COUNTER                  ; E0                    ; Untyped                   ;
; CLK7_COUNTER                  ; E1                    ; Untyped                   ;
; CLK8_COUNTER                  ; E2                    ; Untyped                   ;
; CLK9_COUNTER                  ; E3                    ; Untyped                   ;
; L0_TIME_DELAY                 ; 0                     ; Untyped                   ;
; L1_TIME_DELAY                 ; 0                     ; Untyped                   ;
; G0_TIME_DELAY                 ; 0                     ; Untyped                   ;
; G1_TIME_DELAY                 ; 0                     ; Untyped                   ;
; G2_TIME_DELAY                 ; 0                     ; Untyped                   ;
; G3_TIME_DELAY                 ; 0                     ; Untyped                   ;
; E0_TIME_DELAY                 ; 0                     ; Untyped                   ;
; E1_TIME_DELAY                 ; 0                     ; Untyped                   ;
; E2_TIME_DELAY                 ; 0                     ; Untyped                   ;
; E3_TIME_DELAY                 ; 0                     ; Untyped                   ;
; M_TIME_DELAY                  ; 0                     ; Untyped                   ;
; N_TIME_DELAY                  ; 0                     ; Untyped                   ;
; EXTCLK3_COUNTER               ; E3                    ; Untyped                   ;
; EXTCLK2_COUNTER               ; E2                    ; Untyped                   ;
; EXTCLK1_COUNTER               ; E1                    ; Untyped                   ;
; EXTCLK0_COUNTER               ; E0                    ; Untyped                   ;
; ENABLE0_COUNTER               ; L0                    ; Untyped                   ;
; ENABLE1_COUNTER               ; L0                    ; Untyped                   ;
; CHARGE_PUMP_CURRENT           ; 2                     ; Untyped                   ;
; LOOP_FILTER_R                 ;  1.000000             ; Untyped                   ;
; LOOP_FILTER_C                 ; 5                     ; Untyped                   ;
; CHARGE_PUMP_CURRENT_BITS      ; 9999                  ; Untyped                   ;
; LOOP_FILTER_R_BITS            ; 9999                  ; Untyped                   ;
; LOOP_FILTER_C_BITS            ; 9999                  ; Untyped                   ;
; VCO_POST_SCALE                ; 0                     ; Untyped                   ;
; CLK2_OUTPUT_FREQUENCY         ; 0                     ; Untyped                   ;
; CLK1_OUTPUT_FREQUENCY         ; 0                     ; Untyped                   ;
; CLK0_OUTPUT_FREQUENCY         ; 0                     ; Untyped                   ;
; INTENDED_DEVICE_FAMILY        ; Cyclone IV E          ; Untyped                   ;
; PORT_CLKENA0                  ; PORT_UNUSED           ; Untyped                   ;
; PORT_CLKENA1                  ; PORT_UNUSED           ; Untyped                   ;
; PORT_CLKENA2                  ; PORT_UNUSED           ; Untyped                   ;
; PORT_CLKENA3                  ; PORT_UNUSED           ; Untyped                   ;
; PORT_CLKENA4                  ; PORT_UNUSED           ; Untyped                   ;
; PORT_CLKENA5                  ; PORT_UNUSED           ; Untyped                   ;
; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY     ; Untyped                   ;
; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY     ; Untyped                   ;
; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY     ; Untyped                   ;
; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY     ; Untyped                   ;
; PORT_EXTCLK0                  ; PORT_UNUSED           ; Untyped                   ;
; PORT_EXTCLK1                  ; PORT_UNUSED           ; Untyped                   ;
; PORT_EXTCLK2                  ; PORT_UNUSED           ; Untyped                   ;
; PORT_EXTCLK3                  ; PORT_UNUSED           ; Untyped                   ;
; PORT_CLKBAD0                  ; PORT_UNUSED           ; Untyped                   ;
; PORT_CLKBAD1                  ; PORT_UNUSED           ; Untyped                   ;
; PORT_CLK0                     ; PORT_USED             ; Untyped                   ;
; PORT_CLK1                     ; PORT_USED             ; Untyped                   ;
; PORT_CLK2                     ; PORT_USED             ; Untyped                   ;
; PORT_CLK3                     ; PORT_UNUSED           ; Untyped                   ;
; PORT_CLK4                     ; PORT_UNUSED           ; Untyped                   ;
; PORT_CLK5                     ; PORT_UNUSED           ; Untyped                   ;
; PORT_CLK6                     ; PORT_UNUSED           ; Untyped                   ;
; PORT_CLK7                     ; PORT_UNUSED           ; Untyped                   ;
; PORT_CLK8                     ; PORT_UNUSED           ; Untyped                   ;
; PORT_CLK9                     ; PORT_UNUSED           ; Untyped                   ;
; PORT_SCANDATA                 ; PORT_UNUSED           ; Untyped                   ;
; PORT_SCANDATAOUT              ; PORT_UNUSED           ; Untyped                   ;
; PORT_SCANDONE                 ; PORT_UNUSED           ; Untyped                   ;
; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY     ; Untyped                   ;
; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY     ; Untyped                   ;
; PORT_ACTIVECLOCK              ; PORT_UNUSED           ; Untyped                   ;
; PORT_CLKLOSS                  ; PORT_UNUSED           ; Untyped                   ;
; PORT_INCLK1                   ; PORT_UNUSED           ; Untyped                   ;
; PORT_INCLK0                   ; PORT_USED             ; Untyped                   ;
; PORT_FBIN                     ; PORT_UNUSED           ; Untyped                   ;
; PORT_PLLENA                   ; PORT_UNUSED           ; Untyped                   ;
; PORT_CLKSWITCH                ; PORT_UNUSED           ; Untyped                   ;
; PORT_ARESET                   ; PORT_UNUSED           ; Untyped                   ;
; PORT_PFDENA                   ; PORT_UNUSED           ; Untyped                   ;
; PORT_SCANCLK                  ; PORT_UNUSED           ; Untyped                   ;
; PORT_SCANACLR                 ; PORT_UNUSED           ; Untyped                   ;
; PORT_SCANREAD                 ; PORT_UNUSED           ; Untyped                   ;
; PORT_SCANWRITE                ; PORT_UNUSED           ; Untyped                   ;
; PORT_ENABLE0                  ; PORT_CONNECTIVITY     ; Untyped                   ;
; PORT_ENABLE1                  ; PORT_CONNECTIVITY     ; Untyped                   ;
; PORT_LOCKED                   ; PORT_UNUSED           ; Untyped                   ;
; PORT_CONFIGUPDATE             ; PORT_UNUSED           ; Untyped                   ;
; PORT_FBOUT                    ; PORT_CONNECTIVITY     ; Untyped                   ;
; PORT_PHASEDONE                ; PORT_UNUSED           ; Untyped                   ;
; PORT_PHASESTEP                ; PORT_UNUSED           ; Untyped                   ;
; PORT_PHASEUPDOWN              ; PORT_UNUSED           ; Untyped                   ;
; PORT_SCANCLKENA               ; PORT_UNUSED           ; Untyped                   ;
; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED           ; Untyped                   ;
; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY     ; Untyped                   ;
; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY     ; Untyped                   ;
; M_TEST_SOURCE                 ; 5                     ; Untyped                   ;
; C0_TEST_SOURCE                ; 5                     ; Untyped                   ;
; C1_TEST_SOURCE                ; 5                     ; Untyped                   ;
; C2_TEST_SOURCE                ; 5                     ; Untyped                   ;
; C3_TEST_SOURCE                ; 5                     ; Untyped                   ;
; C4_TEST_SOURCE                ; 5                     ; Untyped                   ;
; C5_TEST_SOURCE                ; 5                     ; Untyped                   ;
; C6_TEST_SOURCE                ; 5                     ; Untyped                   ;
; C7_TEST_SOURCE                ; 5                     ; Untyped                   ;
; C8_TEST_SOURCE                ; 5                     ; Untyped                   ;
; C9_TEST_SOURCE                ; 5                     ; Untyped                   ;
; CBXI_PARAMETER                ; PLL_altpll            ; Untyped                   ;
; VCO_FREQUENCY_CONTROL         ; AUTO                  ; Untyped                   ;
; VCO_PHASE_SHIFT_STEP          ; 0                     ; Untyped                   ;
; WIDTH_CLOCK                   ; 5                     ; Signed Integer            ;
; WIDTH_PHASECOUNTERSELECT      ; 4                     ; Untyped                   ;
; USING_FBMIMICBIDIR_PORT       ; OFF                   ; Untyped                   ;
; DEVICE_FAMILY                 ; Cyclone IV E          ; Untyped                   ;
; SCAN_CHAIN_MIF_FILE           ; UNUSED                ; Untyped                   ;
; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF                   ; Untyped                   ;
; AUTO_CARRY_CHAINS             ; ON                    ; AUTO_CARRY                ;
; IGNORE_CARRY_BUFFERS          ; OFF                   ; IGNORE_CARRY              ;
; AUTO_CASCADE_CHAINS           ; ON                    ; AUTO_CASCADE              ;
; IGNORE_CASCADE_BUFFERS        ; OFF                   ; IGNORE_CASCADE            ;
+-------------------------------+-----------------------+---------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0 ;
+------------------------------------+----------------------+---------------------------------+
; Parameter Name                     ; Value                ; Type                            ;
+------------------------------------+----------------------+---------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                         ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                      ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                    ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                    ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                  ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                         ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                         ;
; WIDTH_A                            ; 8                    ; Untyped                         ;
; WIDTHAD_A                          ; 15                   ; Untyped                         ;
; NUMWORDS_A                         ; 25344                ; Untyped                         ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                         ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                         ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                         ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                         ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                         ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                         ;
; WIDTH_B                            ; 8                    ; Untyped                         ;
; WIDTHAD_B                          ; 15                   ; Untyped                         ;
; NUMWORDS_B                         ; 25344                ; Untyped                         ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                         ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                         ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                         ;
; ADDRESS_REG_B                      ; CLOCK1               ; Untyped                         ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                         ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                         ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                         ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                         ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                         ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                         ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                         ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                         ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                         ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                         ;
; RAM_BLOCK_TYPE                     ; M9K                  ; Untyped                         ;
; BYTE_SIZE                          ; 8                    ; Untyped                         ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                         ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                         ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                         ;
; INIT_FILE                          ; UNUSED               ; Untyped                         ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                         ;
; MAXIMUM_DEPTH                      ; 0                    ; Untyped                         ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                         ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                         ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                         ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                         ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                         ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                         ;
; ENABLE_ECC                         ; FALSE                ; Untyped                         ;
; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                ; Untyped                         ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                         ;
; DEVICE_FAMILY                      ; Cyclone IV E         ; Untyped                         ;
; CBXI_PARAMETER                     ; altsyncram_k5f1      ; Untyped                         ;
+------------------------------------+----------------------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_mult:Mult0                     ;
+------------------------------------------------+--------------+---------------------+
; Parameter Name                                 ; Value        ; Type                ;
+------------------------------------------------+--------------+---------------------+
; AUTO_CARRY_CHAINS                              ; ON           ; AUTO_CARRY          ;
; IGNORE_CARRY_BUFFERS                           ; OFF          ; IGNORE_CARRY        ;
; AUTO_CASCADE_CHAINS                            ; ON           ; AUTO_CASCADE        ;
; IGNORE_CASCADE_BUFFERS                         ; OFF          ; IGNORE_CASCADE      ;
; LPM_WIDTHA                                     ; 15           ; Untyped             ;
; LPM_WIDTHB                                     ; 8            ; Untyped             ;
; LPM_WIDTHP                                     ; 23           ; Untyped             ;
; LPM_WIDTHR                                     ; 23           ; Untyped             ;
; LPM_WIDTHS                                     ; 1            ; Untyped             ;
; LPM_REPRESENTATION                             ; UNSIGNED     ; Untyped             ;
; LPM_PIPELINE                                   ; 0            ; Untyped             ;
; LATENCY                                        ; 0            ; Untyped             ;
; INPUT_A_IS_CONSTANT                            ; NO           ; Untyped             ;
; INPUT_B_IS_CONSTANT                            ; YES          ; Untyped             ;
; USE_EAB                                        ; OFF          ; Untyped             ;
; MAXIMIZE_SPEED                                 ; 5            ; Untyped             ;
; DEVICE_FAMILY                                  ; Cyclone IV E ; Untyped             ;
; CARRY_CHAIN                                    ; MANUAL       ; Untyped             ;
; APEX20K_TECHNOLOGY_MAPPER                      ; LUT          ; TECH_MAPPER_APEX20K ;
; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO         ; Untyped             ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0            ; Untyped             ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0            ; Untyped             ;
; CBXI_PARAMETER                                 ; NOTHING      ; Untyped             ;
; INPUT_A_FIXED_VALUE                            ; Bx           ; Untyped             ;
; INPUT_B_FIXED_VALUE                            ; Bx           ; Untyped             ;
; USE_AHDL_IMPLEMENTATION                        ; OFF          ; Untyped             ;
+------------------------------------------------+--------------+---------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_mult:Mult1                     ;
+------------------------------------------------+--------------+---------------------+
; Parameter Name                                 ; Value        ; Type                ;
+------------------------------------------------+--------------+---------------------+
; AUTO_CARRY_CHAINS                              ; ON           ; AUTO_CARRY          ;
; IGNORE_CARRY_BUFFERS                           ; OFF          ; IGNORE_CARRY        ;
; AUTO_CASCADE_CHAINS                            ; ON           ; AUTO_CASCADE        ;
; IGNORE_CASCADE_BUFFERS                         ; OFF          ; IGNORE_CASCADE      ;
; LPM_WIDTHA                                     ; 10           ; Untyped             ;
; LPM_WIDTHB                                     ; 8            ; Untyped             ;
; LPM_WIDTHP                                     ; 18           ; Untyped             ;
; LPM_WIDTHR                                     ; 18           ; Untyped             ;
; LPM_WIDTHS                                     ; 1            ; Untyped             ;
; LPM_REPRESENTATION                             ; UNSIGNED     ; Untyped             ;
; LPM_PIPELINE                                   ; 0            ; Untyped             ;
; LATENCY                                        ; 0            ; Untyped             ;
; INPUT_A_IS_CONSTANT                            ; NO           ; Untyped             ;
; INPUT_B_IS_CONSTANT                            ; YES          ; Untyped             ;
; USE_EAB                                        ; OFF          ; Untyped             ;
; MAXIMIZE_SPEED                                 ; 6            ; Untyped             ;
; DEVICE_FAMILY                                  ; Cyclone IV E ; Untyped             ;
; CARRY_CHAIN                                    ; MANUAL       ; Untyped             ;
; APEX20K_TECHNOLOGY_MAPPER                      ; LUT          ; TECH_MAPPER_APEX20K ;
; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO         ; Untyped             ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0            ; Untyped             ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0            ; Untyped             ;
; CBXI_PARAMETER                                 ; NOTHING      ; Untyped             ;
; INPUT_A_FIXED_VALUE                            ; Bx           ; Untyped             ;
; INPUT_B_FIXED_VALUE                            ; Bx           ; Untyped             ;
; USE_AHDL_IMPLEMENTATION                        ; OFF          ; Untyped             ;
+------------------------------------------------+--------------+---------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------+
; altpll Parameter Settings by Entity Instance                         ;
+-------------------------------+--------------------------------------+
; Name                          ; Value                                ;
+-------------------------------+--------------------------------------+
; Number of entity instances    ; 1                                    ;
; Entity Instance               ; PLL:PLL_inst|altpll:altpll_component ;
;     -- OPERATION_MODE         ; NORMAL                               ;
;     -- PLL_TYPE               ; AUTO                                 ;
;     -- PRIMARY_CLOCK          ; INCLK0                               ;
;     -- INCLK0_INPUT_FREQUENCY ; 20000                                ;
;     -- INCLK1_INPUT_FREQUENCY ; 0                                    ;
;     -- VCO_MULTIPLY_BY        ; 0                                    ;
;     -- VCO_DIVIDE_BY          ; 0                                    ;
+-------------------------------+--------------------------------------+


+----------------------------------------------------------------------------------------+
; altsyncram Parameter Settings by Entity Instance                                       ;
+-------------------------------------------+--------------------------------------------+
; Name                                      ; Value                                      ;
+-------------------------------------------+--------------------------------------------+
; Number of entity instances                ; 1                                          ;
; Entity Instance                           ; Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0 ;
;     -- OPERATION_MODE                     ; DUAL_PORT                                  ;
;     -- WIDTH_A                            ; 8                                          ;
;     -- NUMWORDS_A                         ; 25344                                      ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                               ;
;     -- WIDTH_B                            ; 8                                          ;
;     -- NUMWORDS_B                         ; 25344                                      ;
;     -- ADDRESS_REG_B                      ; CLOCK1                                     ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                               ;
;     -- RAM_BLOCK_TYPE                     ; M9K                                        ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                  ;
+-------------------------------------------+--------------------------------------------+


+--------------------------------------------------------+
; lpm_mult Parameter Settings by Entity Instance         ;
+---------------------------------------+----------------+
; Name                                  ; Value          ;
+---------------------------------------+----------------+
; Number of entity instances            ; 2              ;
; Entity Instance                       ; lpm_mult:Mult0 ;
;     -- LPM_WIDTHA                     ; 15             ;
;     -- LPM_WIDTHB                     ; 8              ;
;     -- LPM_WIDTHP                     ; 23             ;
;     -- LPM_REPRESENTATION             ; UNSIGNED       ;
;     -- INPUT_A_IS_CONSTANT            ; NO             ;
;     -- INPUT_B_IS_CONSTANT            ; YES            ;
;     -- USE_EAB                        ; OFF            ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO           ;
;     -- INPUT_A_FIXED_VALUE            ; Bx             ;
;     -- INPUT_B_FIXED_VALUE            ; Bx             ;
; Entity Instance                       ; lpm_mult:Mult1 ;
;     -- LPM_WIDTHA                     ; 10             ;
;     -- LPM_WIDTHB                     ; 8              ;
;     -- LPM_WIDTHP                     ; 18             ;
;     -- LPM_REPRESENTATION             ; UNSIGNED       ;
;     -- INPUT_A_IS_CONSTANT            ; NO             ;
;     -- INPUT_B_IS_CONSTANT            ; YES            ;
;     -- USE_EAB                        ; OFF            ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO           ;
;     -- INPUT_A_FIXED_VALUE            ; Bx             ;
;     -- INPUT_B_FIXED_VALUE            ; Bx             ;
+---------------------------------------+----------------+


+------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "IMAGE_PROCESSOR:proc"                                                                 ;
+--------+--------+----------+-------------------------------------------------------------------------------------+
; Port   ; Type   ; Severity ; Details                                                                             ;
+--------+--------+----------+-------------------------------------------------------------------------------------+
; RESULT ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+--------+--------+----------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-----------------------+-----------------------------+
; Type                  ; Count                       ;
+-----------------------+-----------------------------+
; boundary_port         ; 51                          ;
; cycloneiii_ff         ; 59                          ;
;     ENA               ; 8                           ;
;     ENA SCLR          ; 36                          ;
;     SCLR              ; 10                          ;
;     plain             ; 5                           ;
; cycloneiii_lcell_comb ; 173                         ;
;     arith             ; 78                          ;
;         2 data inputs ; 48                          ;
;         3 data inputs ; 30                          ;
;     normal            ; 95                          ;
;         0 data inputs ; 1                           ;
;         1 data inputs ; 7                           ;
;         2 data inputs ; 20                          ;
;         3 data inputs ; 19                          ;
;         4 data inputs ; 48                          ;
; cycloneiii_pll        ; 1                           ;
; cycloneiii_ram_block  ; 32                          ;
;                       ;                             ;
; Max LUT depth         ; 5.60                        ;
; Average LUT depth     ; 3.01                        ;
+-----------------------+-----------------------------+


+-------------------------------+
; Elapsed Time Per Partition    ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top            ; 00:00:01     ;
+----------------+--------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
    Info: Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition
    Info: Processing started: Thu Aug 09 00:24:25 2018
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE0_NANO -c DE0_NANO
Warning (125092): Tcl Script File DE_NANO_SOPC.qip not found
    Info (125063): set_global_assignment -name QIP_FILE DE_NANO_SOPC.qip
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file vga_driver.v
    Info (12023): Found entity 1: VGA_DRIVER File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/VGA_DRIVER.v Line: 14
Info (12021): Found 1 design units, including 1 entities, in source file de0_nano.v
    Info (12023): Found entity 1: DE0_NANO File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 4
Info (12021): Found 1 design units, including 1 entities, in source file dual_port_ram_m9k.v
    Info (12023): Found entity 1: Dual_Port_RAM_M9K File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/Dual_Port_RAM_M9K.v Line: 4
Info (12021): Found 1 design units, including 1 entities, in source file image_processor.v
    Info (12023): Found entity 1: IMAGE_PROCESSOR File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/IMAGE_PROCESSOR.v Line: 6
Info (12021): Found 1 design units, including 1 entities, in source file myfirstpll.v
    Info (12023): Found entity 1: myfirstpll File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/myfirstpll.v Line: 40
Info (12021): Found 1 design units, including 1 entities, in source file pll.v
    Info (12023): Found entity 1: PLL File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/PLL.v Line: 40
Info (12127): Elaborating entity "DE0_NANO" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at DE0_NANO.v(40): truncated value with size 32 to match size of target (15) File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 40
Warning (10230): Verilog HDL assignment warning at DE0_NANO.v(165): truncated value with size 32 to match size of target (15) File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 165
Warning (10034): Output port "GPIO_0_D[33..24]" at DE0_NANO.v(26) has no driver File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 26
Warning (10034): Output port "GPIO_0_D[22]" at DE0_NANO.v(26) has no driver File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 26
Warning (10034): Output port "GPIO_0_D[20]" at DE0_NANO.v(26) has no driver File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 26
Warning (10034): Output port "GPIO_0_D[18]" at DE0_NANO.v(26) has no driver File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 26
Warning (10034): Output port "GPIO_0_D[16]" at DE0_NANO.v(26) has no driver File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 26
Warning (10034): Output port "GPIO_0_D[14]" at DE0_NANO.v(26) has no driver File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 26
Warning (10034): Output port "GPIO_0_D[12]" at DE0_NANO.v(26) has no driver File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 26
Warning (10034): Output port "GPIO_0_D[10]" at DE0_NANO.v(26) has no driver File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 26
Warning (10034): Output port "GPIO_0_D[8]" at DE0_NANO.v(26) has no driver File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 26
Warning (10034): Output port "GPIO_0_D[6]" at DE0_NANO.v(26) has no driver File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 26
Warning (10034): Output port "GPIO_0_D[4..2]" at DE0_NANO.v(26) has no driver File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 26
Info (12128): Elaborating entity "PLL" for hierarchy "PLL:PLL_inst" File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 81
Info (12128): Elaborating entity "altpll" for hierarchy "PLL:PLL_inst|altpll:altpll_component" File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/PLL.v Line: 99
Info (12130): Elaborated megafunction instantiation "PLL:PLL_inst|altpll:altpll_component" File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/PLL.v Line: 99
Info (12133): Instantiated megafunction "PLL:PLL_inst|altpll:altpll_component" with the following parameter: File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/PLL.v Line: 99
    Info (12134): Parameter "bandwidth_type" = "AUTO"
    Info (12134): Parameter "clk0_divide_by" = "25"
    Info (12134): Parameter "clk0_duty_cycle" = "50"
    Info (12134): Parameter "clk0_multiply_by" = "12"
    Info (12134): Parameter "clk0_phase_shift" = "0"
    Info (12134): Parameter "clk1_divide_by" = "2"
    Info (12134): Parameter "clk1_duty_cycle" = "50"
    Info (12134): Parameter "clk1_multiply_by" = "1"
    Info (12134): Parameter "clk1_phase_shift" = "0"
    Info (12134): Parameter "clk2_divide_by" = "1"
    Info (12134): Parameter "clk2_duty_cycle" = "50"
    Info (12134): Parameter "clk2_multiply_by" = "1"
    Info (12134): Parameter "clk2_phase_shift" = "0"
    Info (12134): Parameter "compensate_clock" = "CLK0"
    Info (12134): Parameter "inclk0_input_frequency" = "20000"
    Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
    Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=PLL"
    Info (12134): Parameter "lpm_type" = "altpll"
    Info (12134): Parameter "operation_mode" = "NORMAL"
    Info (12134): Parameter "pll_type" = "AUTO"
    Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
    Info (12134): Parameter "port_areset" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
    Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
    Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
    Info (12134): Parameter "port_inclk0" = "PORT_USED"
    Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_locked" = "PORT_UNUSED"
    Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
    Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
    Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk0" = "PORT_USED"
    Info (12134): Parameter "port_clk1" = "PORT_USED"
    Info (12134): Parameter "port_clk2" = "PORT_USED"
    Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
    Info (12134): Parameter "width_clock" = "5"
Info (12021): Found 1 design units, including 1 entities, in source file db/pll_altpll.v
    Info (12023): Found entity 1: PLL_altpll File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/db/pll_altpll.v Line: 30
Info (12128): Elaborating entity "PLL_altpll" for hierarchy "PLL:PLL_inst|altpll:altpll_component|PLL_altpll:auto_generated" File: c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/altpll.tdf Line: 898
Info (12128): Elaborating entity "Dual_Port_RAM_M9K" for hierarchy "Dual_Port_RAM_M9K:mem" File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 92
Warning (10036): Verilog HDL or VHDL warning at Dual_Port_RAM_M9K.v(34): object "r_addr_reg" assigned a value but never read File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/Dual_Port_RAM_M9K.v Line: 34
Info (12128): Elaborating entity "VGA_DRIVER" for hierarchy "VGA_DRIVER:driver" File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 104
Warning (10230): Verilog HDL assignment warning at VGA_DRIVER.v(71): truncated value with size 32 to match size of target (10) File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/VGA_DRIVER.v Line: 71
Warning (10230): Verilog HDL assignment warning at VGA_DRIVER.v(75): truncated value with size 32 to match size of target (10) File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/VGA_DRIVER.v Line: 75
Info (12128): Elaborating entity "IMAGE_PROCESSOR" for hierarchy "IMAGE_PROCESSOR:proc" File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 114
Warning (10858): Verilog HDL warning at IMAGE_PROCESSOR.v(41): object square_detect used but never assigned File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/IMAGE_PROCESSOR.v Line: 41
Warning (10858): Verilog HDL warning at IMAGE_PROCESSOR.v(42): object circle_detect used but never assigned File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/IMAGE_PROCESSOR.v Line: 42
Warning (10030): Net "square_detect" at IMAGE_PROCESSOR.v(41) has no driver or initial value, using a default initial value '0' File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/IMAGE_PROCESSOR.v Line: 41
Warning (10030): Net "circle_detect" at IMAGE_PROCESSOR.v(42) has no driver or initial value, using a default initial value '0' File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/IMAGE_PROCESSOR.v Line: 42
Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "RGB_pixel_count" into its bus
Warning (276027): Inferred dual-clock RAM node "Dual_Port_RAM_M9K:mem|mem_rtl_0" from synchronous design logic.  The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design.
Info (19000): Inferred 1 megafunctions from design logic
    Info (276029): Inferred altsyncram megafunction from the following design logic: "Dual_Port_RAM_M9K:mem|mem_rtl_0" 
        Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
        Info (286033): Parameter WIDTH_A set to 8
        Info (286033): Parameter WIDTHAD_A set to 15
        Info (286033): Parameter NUMWORDS_A set to 25344
        Info (286033): Parameter WIDTH_B set to 8
        Info (286033): Parameter WIDTHAD_B set to 15
        Info (286033): Parameter NUMWORDS_B set to 25344
        Info (286033): Parameter ADDRESS_ACLR_A set to NONE
        Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
        Info (286033): Parameter ADDRESS_ACLR_B set to NONE
        Info (286033): Parameter OUTDATA_ACLR_B set to NONE
        Info (286033): Parameter ADDRESS_REG_B set to CLOCK1
        Info (286033): Parameter INDATA_ACLR_A set to NONE
        Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
        Info (286033): Parameter RAM_BLOCK_TYPE set to M9K
Info (278001): Inferred 2 megafunctions from design logic
    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "Mult0" File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 40
    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "Mult1" File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 165
Info (12130): Elaborated megafunction instantiation "Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0"
Info (12133): Instantiated megafunction "Dual_Port_RAM_M9K:mem|altsyncram:mem_rtl_0" with the following parameter:
    Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT"
    Info (12134): Parameter "WIDTH_A" = "8"
    Info (12134): Parameter "WIDTHAD_A" = "15"
    Info (12134): Parameter "NUMWORDS_A" = "25344"
    Info (12134): Parameter "WIDTH_B" = "8"
    Info (12134): Parameter "WIDTHAD_B" = "15"
    Info (12134): Parameter "NUMWORDS_B" = "25344"
    Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
    Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED"
    Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE"
    Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE"
    Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK1"
    Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
    Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
    Info (12134): Parameter "RAM_BLOCK_TYPE" = "M9K"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_k5f1.tdf
    Info (12023): Found entity 1: altsyncram_k5f1 File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/db/altsyncram_k5f1.tdf Line: 34
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_msa.tdf
    Info (12023): Found entity 1: decode_msa File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/db/decode_msa.tdf Line: 23
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_f8a.tdf
    Info (12023): Found entity 1: decode_f8a File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/db/decode_f8a.tdf Line: 23
Info (12021): Found 1 design units, including 1 entities, in source file db/mux_6nb.tdf
    Info (12023): Found entity 1: mux_6nb File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/db/mux_6nb.tdf Line: 23
Info (12130): Elaborated megafunction instantiation "lpm_mult:Mult0" File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 40
Info (12133): Instantiated megafunction "lpm_mult:Mult0" with the following parameter: File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 40
    Info (12134): Parameter "LPM_WIDTHA" = "15"
    Info (12134): Parameter "LPM_WIDTHB" = "8"
    Info (12134): Parameter "LPM_WIDTHP" = "23"
    Info (12134): Parameter "LPM_WIDTHR" = "23"
    Info (12134): Parameter "LPM_WIDTHS" = "1"
    Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
    Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "YES"
    Info (12134): Parameter "MAXIMIZE_SPEED" = "5"
Info (12131): Elaborated megafunction instantiation "lpm_mult:Mult0|multcore:mult_core", which is child of megafunction instantiation "lpm_mult:Mult0" File: c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/lpm_mult.tdf Line: 309
Info (12131): Elaborated megafunction instantiation "lpm_mult:Mult0|multcore:mult_core|mpar_add:padder", which is child of megafunction instantiation "lpm_mult:Mult0" File: c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/multcore.tdf Line: 229
Info (12131): Elaborated megafunction instantiation "lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]", which is child of megafunction instantiation "lpm_mult:Mult0" File: c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/mpar_add.tdf Line: 78
Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_lgh.tdf
    Info (12023): Found entity 1: add_sub_lgh File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/db/add_sub_lgh.tdf Line: 23
Info (12131): Elaborated megafunction instantiation "lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add", which is child of megafunction instantiation "lpm_mult:Mult0" File: c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/mpar_add.tdf Line: 138
Info (12131): Elaborated megafunction instantiation "lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]", which is child of megafunction instantiation "lpm_mult:Mult0" File: c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/mpar_add.tdf Line: 78
Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_pgh.tdf
    Info (12023): Found entity 1: add_sub_pgh File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/db/add_sub_pgh.tdf Line: 23
Info (12131): Elaborated megafunction instantiation "lpm_mult:Mult0|altshift:external_latency_ffs", which is child of megafunction instantiation "lpm_mult:Mult0" File: c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/lpm_mult.tdf Line: 352
Info (12130): Elaborated megafunction instantiation "lpm_mult:Mult1" File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 165
Info (12133): Instantiated megafunction "lpm_mult:Mult1" with the following parameter: File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 165
    Info (12134): Parameter "LPM_WIDTHA" = "10"
    Info (12134): Parameter "LPM_WIDTHB" = "8"
    Info (12134): Parameter "LPM_WIDTHP" = "18"
    Info (12134): Parameter "LPM_WIDTHR" = "18"
    Info (12134): Parameter "LPM_WIDTHS" = "1"
    Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
    Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "YES"
    Info (12134): Parameter "MAXIMIZE_SPEED" = "6"
Info (12131): Elaborated megafunction instantiation "lpm_mult:Mult1|multcore:mult_core", which is child of megafunction instantiation "lpm_mult:Mult1" File: c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/lpm_mult.tdf Line: 309
Info (12131): Elaborated megafunction instantiation "lpm_mult:Mult1|multcore:mult_core|mpar_add:padder", which is child of megafunction instantiation "lpm_mult:Mult1" File: c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/multcore.tdf Line: 229
Info (12131): Elaborated megafunction instantiation "lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]", which is child of megafunction instantiation "lpm_mult:Mult1" File: c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/mpar_add.tdf Line: 78
Info (12131): Elaborated megafunction instantiation "lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add", which is child of megafunction instantiation "lpm_mult:Mult1" File: c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/mpar_add.tdf Line: 138
Info (12131): Elaborated megafunction instantiation "lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]", which is child of megafunction instantiation "lpm_mult:Mult1" File: c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/mpar_add.tdf Line: 78
Info (12131): Elaborated megafunction instantiation "lpm_mult:Mult1|altshift:external_latency_ffs", which is child of megafunction instantiation "lpm_mult:Mult1" File: c:/intelfpga_lite/17.0/quartus/libraries/megafunctions/lpm_mult.tdf Line: 352
Warning (13024): Output pins are stuck at VCC or GND
    Warning (13410): Pin "GPIO_0_D[2]" is stuck at GND File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 26
    Warning (13410): Pin "GPIO_0_D[3]" is stuck at GND File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 26
    Warning (13410): Pin "GPIO_0_D[4]" is stuck at GND File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 26
    Warning (13410): Pin "GPIO_0_D[6]" is stuck at GND File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 26
    Warning (13410): Pin "GPIO_0_D[8]" is stuck at GND File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 26
    Warning (13410): Pin "GPIO_0_D[10]" is stuck at GND File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 26
    Warning (13410): Pin "GPIO_0_D[12]" is stuck at GND File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 26
    Warning (13410): Pin "GPIO_0_D[14]" is stuck at GND File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 26
    Warning (13410): Pin "GPIO_0_D[16]" is stuck at GND File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 26
    Warning (13410): Pin "GPIO_0_D[18]" is stuck at GND File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 26
    Warning (13410): Pin "GPIO_0_D[20]" is stuck at GND File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 26
    Warning (13410): Pin "GPIO_0_D[22]" is stuck at GND File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 26
    Warning (13410): Pin "GPIO_0_D[24]" is stuck at GND File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 26
    Warning (13410): Pin "GPIO_0_D[25]" is stuck at GND File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 26
    Warning (13410): Pin "GPIO_0_D[26]" is stuck at GND File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 26
    Warning (13410): Pin "GPIO_0_D[27]" is stuck at GND File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 26
    Warning (13410): Pin "GPIO_0_D[28]" is stuck at GND File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 26
    Warning (13410): Pin "GPIO_0_D[29]" is stuck at GND File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 26
    Warning (13410): Pin "GPIO_0_D[30]" is stuck at GND File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 26
    Warning (13410): Pin "GPIO_0_D[31]" is stuck at GND File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 26
    Warning (13410): Pin "GPIO_0_D[32]" is stuck at GND File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 26
    Warning (13410): Pin "GPIO_0_D[33]" is stuck at GND File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 26
Info (286030): Timing-Driven Synthesis is running
Info (17049): 4 registers lost all their fanouts during netlist optimizations.
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL
Warning (21074): Design contains 4 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "GPIO_1_D[28]" File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 28
    Warning (15610): No output dependent on input pin "GPIO_1_D[29]" File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 28
    Warning (15610): No output dependent on input pin "GPIO_1_D[31]" File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 28
    Warning (15610): No output dependent on input pin "KEY[1]" File: C:/Users/labuser/Desktop/jd794/CV-with-FPGA/OV7670_template/DE0_NANO.v Line: 29
Info (21057): Implemented 269 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 17 input pins
    Info (21059): Implemented 34 output pins
    Info (21061): Implemented 185 logic cells
    Info (21064): Implemented 32 RAM segments
    Info (21065): Implemented 1 PLLs
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 51 warnings
    Info: Peak virtual memory: 675 megabytes
    Info: Processing ended: Thu Aug 09 00:24:37 2018
    Info: Elapsed time: 00:00:12
    Info: Total CPU time (on all processors): 00:00:24


